A. Field of the Invention
This invention pertains to data processing systems. In particular, this invention relates to processor memory recall systems for examination of addresses being executed within the processor or its related peripheral controllers.
B. Prior Art
Systems for stopping a data processing system at a particular memory address are known in the art. However, in some prior systems, only the particular memory address location is stored within such systems and provision made for stopping the processor at the particular address. These prior systems do not permit examination of multiple memory addresses being executed in the processor system and thus, the operator is not allowed to trace the execution path of the processor system.
In some prior cases, software has been used to provide examination of several processor memory address locations. However, in this use of software the examination could not be done in a real time environment and consequently, this increased the examination time by the operator. Further, such prior software systems would not allow examination of memory addresses being executed in the processor during input-output operations by the processor systems. Utilization of prior software systems only permitted address location stopping when the processor was in control. This severely limited the memory address examination procedure to specific condition states of the processor system.